The present application relates generally to tunnel field-effect transistor (TFET) devices, and more specifically to heterojunction TFETs and their methods of manufacture.
Operation of a tunnel field-effect transistor is based on electron tunneling, which, in principle, is capable of switching on and off below the theoretical subthreshold swing (SS) of 60 mV/decade at room temperature that is attributable to thermionic carrier injection in the case of a conventional metal oxide semiconductor field effect transistor (MOSFET). The use of TFETs is therefore expected to reduce the power consumption of electronic devices.
A TFET device structure includes a p-i-n (p-type, intrinsic, n-type) junction wherein the electrostatic potential of the intrinsic region is controlled by a gate terminal. The device is operated by applying a gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, band-to-band tunneling (BTBT) occurs as the conduction band of the intrinsic region aligns with the valence band of the p-type region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and currents flow across the device. When the gate bias is reduced, the bands become misaligned and the current flow ceases.
In view of the short-channel effect, off leakage current suppression of nanowire FETs, and their capability of providing a subthreshold swing that is not limited to kT/q (where k is the Boltzmann constant, T is absolute temperature, and q is the magnitude of the electrical charge on an electron), such devices have become candidates for the next-generation very large scale integration (VLSI) device. In view of the foregoing, it would be advantageous to provide a nanowire TFET whose structure and method of manufacture are readily fabricated with complementary metal oxide semiconductor (CMOS) compatible technology.